Hardware

Boards for the gaps nobody fills

Five open designs, all born on a gig — a DMX node that daisy-chains on one Cat5, a bridge that lets a control app you already own drive amplifiers it was never sold to talk to, a video mainframe, a mixing console computed in FPGA fabric, and a coupler that quietly extends a cat6a run past spec.

Where these actually are: designed, simulated and reviewed — not yet proven on a bench. Each board says exactly what has and hasn't been run on real hardware. We would rather you knew.

Lighting · Art-Net / sACN to DMX512

nanODE

Board v0.4.0 · routing in progress

A PoE-powered, daisy-chainable Art-Net / sACN to 4x DMX512 node. One Cat5 in, one loop out - power and data - so a run of nodes needs a single cable from the switch, not one per box.

4 universes out5-pin XLR, from Art-Net 4 (including ArtSync) or sACN / E1.31.
Real RDM discoveryRuns as a background task, so the web console never blocks on it.
Daisy-chain built inInternal 3-port switch: Cat5 in, loop out, plus the ESP32 itself.
Field-replaceable portsEvery external connector is a daughter-card. Smash an XLR on site, swap it without a soldering iron.
Browser consoleOver WiFi or Ethernet - patch, address, and see RDM devices live.

Honest status

Firmware builds clean against real ESP-IDF 5.5 tooling, and the REST API and RDM discovery are verified against a mock node - but this has never run on real silicon. The board render predates the current layout.

nanODE main board render, rev B, top view — Main board, rev B render

nanODE browser console showing DMX universes and RDM discovery — The browser console

MCU: ESP32
Network: Internal 3-port switch, PoE
Outputs: 4 x DMX512 on 5-pin XLR
Protocols: Art-Net 4, sACN / E1.31, RDM
Enclosure: Aluminium extrusion, laser-cut acrylic ends
Repo: Private

Audio · IP and USB to CAN bus converter

dbCANary

Rev A fab-ready · prototypes in build

An IP and USB to CAN bus converter for use with the d&b amplifier ecosystem. It puts amplifiers that only speak CAN onto the network, so the control software you already run can discover and drive them - through hardware you can build yourself.

Transparent bridgeNo interpretation and no extra protocol layer. The gateway is invisible to the control application, which is the entire point of it.
Protocol solvedVerified against the real control software: it is discovered, it connects, and it drives the bus.
Standard partsESP32-S3, W5500 Ethernet, ADM3053 isolated CAN. Nothing exotic, nothing unobtainable.
Bench test rigA board self-test image, a test script that runs in simulation, and generated probe-point renders for bring-up.

Honest status

The protocol work is verified against real hardware and rev A is DRC-clean with gerbers exported - but the firmware has never executed on a board. Bring-up starts when the prototypes land.

dbCANary rev A board, isometric render — Rev A board, isometric render

dbCANary rev A board, top view render — Top view

MCU: ESP32-S3
Network: W5500 Ethernet
Bus: ADM3053 isolated CAN, 100 kbit/s
Role: IP and USB to CAN bus converter
For: The d&b amplifier ecosystem
Repo: Private

Video · Modular AV processing mainframe

OpenAVSwitch

Phase 1 design · RTL in simulation

An open, modular AV processing mainframe: many simultaneous inputs, multi-layer real-time compositing and scaling, and seamless switching - built on commodity FPGA SoCs instead of closed, proprietary hardware.

Phase 1 is deliberately smallA 4-in / 1-out HDMI 4K seamless switcher. Prove the pipeline before scaling the frame.
Compositing in fabricMulti-layer scaling and mixing on Zynq UltraScale+, not on a GPU that has to be scheduled.
Seamless by constructionSwitching happens inside the video pipeline, so there is no black frame to hide.
Modular frameInput, output and processing as separate cards, so the frame grows rather than being replaced.

Honest status

Design and RTL only. Nothing here has been through professional design review or run on real hardware - it exists in simulation. Read the RTL critically before relying on any of it.

OpenAVSwitch Phase 1 blueprint: four HDMI inputs into a compositing pipeline and one HDMI output — Phase 1 blueprint

Platform: Xilinx Zynq UltraScale+ SoC
Phase 1: 4-in / 1-out HDMI, 4K
Class: Large-format live video processor
Language: SystemVerilog
Repo: Private

Audio · FPGA-native live mixing console

LOOM

DSP core bit-exact under Verilator

An open, FPGA-native live mixing console. 128 inputs, 64 buses, every channel strip computed in fabric at 96 kHz - speaking Dante, RAVENNA/AES67 and AVB/Milan simultaneously, with an x86 sidecar for VST3 hosting and NPU-accelerated ML audio.

Everything in fabric128 in, 64 bus, 32-bit fixed-point Q4.27 with a 59-bit accumulator. No DSP chips to run out of.
Three AoIP stacks at onceDante native on-die, AES67/RAVENNA and AVB/Milan in the PL - concurrently, not one at a time.
Latency-aligned routingA full 192x64 crosspoint where any input reaches any output in the same sample count, whatever the route depth.
Verified, not assertedA fixed-point Rust reference model pins the arithmetic, and the SystemVerilog is checked bit-exact against it.
A smart layer that is optionalML feedback prediction and noise reduction on a Hailo-8, fed feature vectors computed in fabric.

Honest status

The fixed-point model and the biquad and TDM cores are built and verified bit-exact under Verilator. That is a long way from a console: no board exists, and nothing has run on an FPGA.

LOOM — No render yet — design is on paper and in simulation

Platform: AMD Zynq UltraScale+ XCZU7EV (ZCU106)
Channels: 128 in / 64 bus @ 96 kHz
Format: Q4.27 fixed-point, 59-bit accumulator
AoIP: Dante + AES67/RAVENNA + Milan
Local I/O: 192 in / 192 out (analog, AES3, MADI)
Repo: Private

Infrastructure · Inline 10GBASE-T regenerator

etherCON 10G PoE Repeater

Feasibility closed · schematic capture

An inline, fanless Layer-1 10GBASE-T repeater with managed pass-through PoE, built into a shell the size of a Neutrik NE8FF feedthrough. Its job is to reset the 100 m cabling budget so a cat6a run can be extended past spec by dropping a unit in mid-run.

Not a booster10GBASE-T can't be analog-amplified. The link is fully terminated in a PHY and re-transmitted, which resets the distance budget and hands the far end a fresh eye.
Invisible to the networkNo MAC, no switch fabric, no store-and-forward - so it is transparent to L2/L3 and, critically, to PTP. It looks like a slightly longer cable.
PoE passes through, managedAn 802.3bt PD front-end feeding an 802.3bt PSE, so power crosses the joint under supervision rather than by accident.
Fits the shell it has to fitTwo AQR113C PHYs host-to-host over fixed 10G XFI on a ~119 mm board, inside a finned extrusion the size of the coupler it replaces.

Honest status

Electronics feasibility is closed with margin and the thermal budget is written down. The KiCad project has both PHY sheets wired, but the remaining risk is mechanical fit - and no board has been made.

Block diagram: etherCON A to MagJack to AQR113C PHY A over XFI to PHY B to MagJack to etherCON B, supervised over MDIO, with an 802.3bt PD front-end feeding a managed PSE — Data and power path

PHYs: 2x Marvell AQR113C, host-to-host XFI
Rate: 10GBASE-T, fixed 10G
Magnetics: Bel 10G PoE MagJack
Power: 802.3bt PD in, 802.3bt PSE out
Board: ~119 mm, NE8FF-size finned extrusion
Repo: Private

More hardware

There's a queue behind these

A touring control surface for the desk. A bespoke surface for the dMix 128. An in-house PCB assembly line so these stop being quotes from someone else. They are at various stages of not-being-finished, and they surface here as they get close enough to show.

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